Basic operation principles of associate co-processor module for specialized computer systems based on programmable logical integral schemes

Abstract

Nowadays, the main field of computer application is the work with large volumes (arrays) of data, where the operations of all sorts of searches and sorting are the most complex ones. Existing computing systems use the address memory architecture. With such an organization, it is necessary to read each memory module address and compare it with the search argument in order to search for data in memory. Thus a lot of computer time is needed to search for the necessary information in memory. This circumstance affects the speed of the computer system as a whole. The paper considers the possibility of an associative coprocessor module implementation for specialized computer systems using a modern element base. The purpose of the article is to develop and to study the module of an associative coprocessor based on FPGA for specialized computing, for example, multiprocessor systems that perform associative functions and data storage functions. The object of this article development and research is an associative coprocessor based on FPGA. To achieve the goals set in the work, the Xilinx Web Pack CAD system was used with the ability to create and simulate the work of the device using a schematic editor and VHDL language, which greatly facilitates the synthesis of projects for the use on a modern element base - FPGA. The result of the research is VHDL codes of the associative coprocessor module and its individual blocks have been developed and debugged. The device functionality and performance was verified by CAD system testing used during the work, and time charts were obtained. The results of the study are the received VHDL codes of the associative coprocessor module, from which the firmware file was synthesized for FPGA configuring.  Key words : memory addressing, associative memory, module, bus interface, computer system, coprocessor, hardware implementation, memory cell, multiple coincidence analyzer, record cycle, read cycle.